1. Field of the Invention
The present invention relates to on chip voltage generation techniques for producing a voltage on chip which is outside the range of a power supply voltage supplied to the chip; and more particularly to the generation of wordline voltages on low power memory devices like flash memory, mask ROM, and SRAM, where the power supply voltage may be less than the read potential required for sensing data in the memory.
2. Description of Related Art
Integrated circuits have in the past been manufactured in order to work with a power supply voltage of about 5 volts, within a specified range of +/-10%. Of course other power supply voltages have been utilized. There is a current trend for many applications to design integrated circuits to work with lower power supply voltages. Lower voltages generally result in lower power operation for the devices, and are easier to supply using batteries in small devices. For example, one low supply voltage which is emerging as a standard is specified to operate over a range of about 2.7 to 3.6 volts. Other standards are being developed around even lower voltages.
On chip circuits however are often designed to operate at higher voltages for some purposes. For example, in memory devices, such as flash memory, wordlines which supply a gate potential to memory cells are often designed to operate at a read potential of 4 volts or more. Thus, the low power supply voltage is insufficient to supply directly an on chip voltage high enough to drive the wordlines. This problem is dealt with by including charge pumps or other voltage supply boosters on the integrated circuits in order to supply the higher working voltages on chip. See for example U.S. Pat. No. 5,511,026 entitled BOOSTED AND REGULATED GATE POWER SUPPLY WITH REFERENCE TRACKING FOR MULTI-DENSITY AND LOW VOLTAGE SUPPLY MEMORIES. The '026 patent describes an integrated circuit memory having charge pumps configured to supply wordline voltages at a level higher than the supply potential. Furthermore, the '026 patent describes the use of on chip charge pumps to provide a plurality of wordline voltages for multi-level/memory devices, so that a greater working margin is provided between the memory cell states, than would be normally available using a standard supply potential.
One problem associated with the prior art approaches to on chip charge pumps for these purposes arises from the difficulty of producing a well regulated output level without sacrificing speed. Well regulated levels are particularly important in multiple level per cell memory devices, or low voltage devices which operate with a narrow margin for the read voltage. However, it is desirable to read quickly. The time required to settle a charge pump output on a well regulated level can contribute a significant portion of delay to a read operation, or other operation requiring a charge pump generated output for operation.
Accordingly, it is desirable to provide a on chip voltage supply circuit for use with integrated circuits that provides for more precise control of the on chip voltage and which operates quickly.